Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices. One type of semiconductor device is a semiconductor storage device, such as dynamic random access memories (DRAMs), or flash memories, both of which use charges to store information.
A more recent development in semiconductor memory devices involves spin electronics, which combines semiconductor technology and magnetic materials and devices. The spin polarization of electrons, rather than the charge of the electrons, is used to indicate the state of “1” or “0.” One such spin electronic device is a spin torque transfer (STT) magnetic tunneling junction (MTJ) device 10, as shown in FIG. 1.
MTJ device 10 includes free layer 12, tunnel layer 14, and pinned layer 16. The magnetization direction of free layer 12 can be reversed by applying a current through tunnel layer 14, which causes the injected polarized electrons within free layer 12 to exert so-called spin torques on the magnetization of free layer 12. Pinned layer 16 has a fixed magnetization direction. When current I1 flows in the direction from free layer 12 to pinned layer 16, electrons flow in a reverse direction, that is, from pinned layer 16 to free layer 12. The electrons are polarized to the same magnetization direction of pinned layer 16 after passing pinned layer 16, flowing through tunnel layer 14, and then flowing into and accumulating in free layer 12. Eventually, the magnetization of free layer 12 is parallel to that of pinned layer 16, and MTJ device 10 will be at a low resistance state. The electron injection caused by current I1 is referred to as a major injection.
When current I2 flowing from pinned layer 16 to free layer 12 is applied, electrons flow in the direction from free layer 12 to pinned layer 16. The electrons having the same polarization as the magnetization direction of pinned layer 16 are able to flow through tunnel layer 14, and into pinned layer 16. Conversely, electrons with polarization differing from the magnetization of pinned layer 16 will be reflected (blocked) by pinned layer 16, and will accumulate in free layer 12. Eventually, magnetization of free layer 12 becomes anti-parallel to that of pinned layer 16, and MTJ device 10 will be at a high-resistance state. The respective electron injection caused by current I2 is referred to as a minor injection.
To eliminate the parasitic loading of MRAM cells, when MRAM cells are integrated in MRAM arrays, selectors are used to electrically isolate the unselected MRAM cells from source lines. For example, FIG. 2 illustrates an MRAM cell including MTJ device 10 and selector 20, which is controlled by word line 22 and connected between bit-line BL and source line SL. When MTJ device 10 is selected for writing or reading, word line 22 is set to logic high, so that writing current I can pass MTJ device 10. The addition of selector 20, however, causes an increase in the chip area per MRAM cell. To reduce the chip area usage of selector 20, selector 20 is typically small. However, this means that writing current I is limited.
The writing of MRAM cells is related to quantum mechanisms, and the probability of a successful writing is related to two factors, writing current I and the pulse width of writing current I. The greater writing current I is and/or the longer the writing pulse is, the greater the possibility of a successful writing. Since selector 20 as shown in FIG. 2 limits writing current I, the pulse width has to be increased. However, with factors such as writing current variation, quantum mechanism, and the possibility of sudden power variation, even if the pulse width is increased, uncertainty still exists in the writing of MRAM cells. As a result, most of the MRAM cells can be written in relatively short writing pulses, while a small amount of MRAM cells require much longer writing time than others. To ensure no failure occurs in the writing, the pulse width has to be so great as to ensure that even the MRAM cell requiring the longest pulse can be successfully written. This means that the pulse width will be significantly greater than the required pulse widths of most of the MRAM cells. The writing time is thus significantly extended. Methods for solving the above-discussed problems are thus needed.